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GALVANTECH, INC. ASYNCHRONOUS SRAM
FEATURES
* * * * * * * * * * * Fast access times: 10, 12 and 15ns Fast OE# access times: 5, 6and 7ns Single +3.3V +0.3V power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Center power and ground pins for greater noise immunity JEDEC standard for functionality and revolutionary pinout Easy memory expansion with CE# and OE# options Automatic CE# power down High-performance, low-power consumption, CMOS double-poly, double-metal process
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
512K x 8 SRAM
+3.3V SUPPLY REVOLUTIONARY PINOUT
GENERAL DESCRIPTION
The GVT73512A8 is organized as a 524,288 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#) and output enable (OE#) with this organization. Writing to these devices is accomplished when write enable (WE#) and chip enable (CE#) inputs are both LOW. Reading is accomplished when (CE#) and (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
OPTIONS
* Timing 10ns access 12ns access 15ns access Packages 36-pin SOJ (400 mil) Temperature Commercial Industrial
MARKING
-10 -12 -15
*
J
A0 A1 A2 A3 A4 CE# DQ1 DQ2 VCC VSS DQ3 DQ4 WE# A5 A6 A7 A8 A9
PIN ASSIGNMENT 36-Pin SOJ
(0C to 70C) (-40C to 85C)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
*
None I
NC A18 A17 A16 A15 OE# DQ8 DQ7 VSS VCC DQ6 DQ5 A14 A13 A12 A11 A10 NC
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
Rev. 7/98
Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
VCC VSS A0 DQ1
ROW DECODER
ADDRESS BUFFER
MEMORY ARRAY 1024 ROWS X 512 X 8 COLUMNS
I/O CONTROL
DQ8
CE# WE#
OE#
A18
COLUMN DECODER
POWER DOWN
TRUTH TABLE
MODE READ WRITE OUTPUT DISABLE STANDBY CE# L L L H WE# H L H X OE# L X H X DQ Q D HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE STANDBY
PIN DESCRIPTIONS
SOJ Pin Numbers
1, 2, 3, 4, 5, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 32, 33, 34, 35 13 6
SYMBOL
A0-A18
TYPE
Input
DESCRIPTION
Addresses Inputs: These inputs determine which cell is addressed.
WE# CE#
Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enable: This active LOW input is used to enable the device. When CE# is LOW, the chip is selected. When CE# is HIGH, the chip is disabled and automatically goes into standby power mode.
Input
31 7, 8,11, 12, 25, 26, 29, 30 9, 27 10, 28
OE# DQ1-DQ8 VCC VSS
Input Output Enable: This active LOW input enables the output drivers. Input/Output SRAM Data I/O: Data inputs and data outputs Supply Supply Power Supply:3.3V +0.3V Ground
July 7, 1998
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.2W Short Circuit Output Current .......................................50mA
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA
CONDITIONS
SYMBOL
VIH VIl ILI ILO VOH VOL VCC
MIN
2.2 -0.5 -5 -5 2.4
MAX
VCC+0.5 0.8 5 5
UNITS
V V uA uA V
NOTES
1, 2 1, 2
1 1 1
0.4 3.0 3.6
V V
DESCRIPTION
Power Supply Current: Operating TTL Standby CMOS Standby
CONDITIONS
Device selected; CE# < VIL; VCC =MAX; f=fMAX; outputs open CE# >VIH; VCC = MAX; f=fMAX CE1# >VCC -0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0
SYM
Icc ISB1 ISB2
TYP
90 30 0.1
-10
240 85 10
-12
210 80 10
-15
175 70 10
UNITS NOTES mA mA mA 3, 14 14 14
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBOL
CI CI/O
MAX
6 8
UNITS
pF pF
NOTES
4 4
July 7, 1998
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V
DESCRIPTION
READ Cycle READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output Enable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE Cycle WRITE cycle time Chip Enable to end of write Address valid to end of write, with OE# HIGH Address setup time Address hold from end of write WRITE pulse width WRITE pulse width, with OE# HIGH Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z
tWC tCW tAW tAS tAH tWP2 tWP1 tDS tDH tLZWE tHZWE tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tPU tPD
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
+0.3V)
- 10 - 12
MIN MAX
- 15
MIN MAX UNITS NOTES
SYM
MIN
MAX
10 10 10 3 3 5 5 0 5 0 10 10 8 8 0 0 10 8 5 0 3 6
12 12 12 3 3 6 6 0 6 0 12 12 8 8 0 0 10 8 6 0 4 6
15 15 15 3 3 7 7 0 7 0 15 15 9 9 0 0 11 9 7 0 5 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 7 4, 6, 7 4, 6 4 4 4, 7 4, 6, 7
July 7, 1998
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
OUTPUT LOADS
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF 30 pF
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tRC /2. VIL -2.0V for t tRC /2
8. 9.
WE# is HIGH for READ cycle. Device is continuously selected. Chip enable and output enables are held in their active state.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE.
10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 3.3V, 25oC and 20ns cycle time.
July 7, 1998
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
VIH VIL
3.0V
t
VDR
3.0V
tRC
CDR
CE#
READ CYCLE NO. 1(8, 9)
tRC
ADDR
tAA tOH
VALID
Q
PREVIOUS DATA VALID
READ CYCLE NO. 2(7, 8, 10, 12)
t
DATA VALID
RC
CE#
tAOE
tLZOE
OE#
tACE tLZCE t
tHZCE
HZOE
Q
HIGH Z
DATA VALID DON'T CARE UNDEFINED
July 7, 1998
6
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW))
t
WC
ADDR
t
AW
t
t
AH
CW
CE#
tAS
tWP2
WE#
tDS tDH
D
tHZWE
DATA VALID
tLZWE
Q
HIGH Z
WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH)
t WC
ADDR
tAW t t AH
CW
CE#
tAS tWP1
WE#
tDS tDH
D Q
DATA VALID HIGH Z DON'T CARE UNDEFINED
July 7, 1998
7
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled)
t
WC
ADDR
tAW t tAH t
AS
CW
CE#
tWP1
WE#
tDS tDH
D
DATA VALID HIGH Z
Q
DON'T CARE
July 7, 1998
8
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98
GALVANTECH, INC.
Package Dimensions
GVT73512A8 REVOLUTIONARY PINOUT 512K X 8
36-pin 400 Mil Plastic SOJ (J)
.941 (23.90) .923 (23.44)
.405 (10.29) .395 (10.03)
.445 (11.30) .435 (11.05)
PIN #1 INDEX
.050 (1.27) TYP
.148 (3.76) .138 (3.51)
.030 (0.76) MIN
SEATING PLANE .020 (0.51) .015 (0.38)
.095 (2.41) .080 (2.03) .380 (9.65) .360 (9.14)
Note: All dimensions in inches (millimeters)
MAX MIN
or typical, min where noted.
Ordering Information GVT 73512A8 XX - XX X
Galvantech Prefix Part Number Temperature (Blank = Commercial I = Industrial) Speed ( 10 = 10ns 12 = 12ns, 15= 15ns) Package (J = 400 mil SOJ)
July 7, 1998
9
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 7/98

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